The present invention relates to the field of network communications, and more particularly, to the testing of an external system memory of a network interface controller.
Local area networks use a network cable or other media to link stations on the network. Each local area network architecture uses a media access controller (MAC) enabling network interface cards at each station to share access to the media.
Conventional local area network architectures use media access controllers operating according to half-duplex or full-duplex Ethernet (ANSI/IEEE standard 802.3) protocol using a described network medium, such as 10 BASE-T. Newer operating systems require that a network station be able to detect the presence of the network. In an Ethernet 10 BASE-T environment, the network is detected by the transmission of a line pulse by the physical layer (PHY) transceiver. The periodic link pulse on the 10 BASE-T media is detected by a PHY receiver, which determines the presence of another network station transmitting on the network medium based on the detection of the periodic link pulses. Hence, a PHY transceiver at station A is able to detect the presence of station B, without the transmission or reception of data packets, by the reception of link pulses on the 10 BASE-T medium from the PHY transmitter at station B.
Architectures have been developed enabling computers to be linked together using conventional twisted pair telephone lines instead of established local area network media such as 10 BASE-T. Such an arrangement, referred herein as a home network environment, provides the advantage that existing telephone wiring in a home may be used to implement a home network environment. However, telephone lines are inherently noisy due to spurious noise caused by electrical devices in the home, for example dimmer switches, transformers of home appliances, etc. In addition, the twisted pair telephone lines suffer turn-on transients due to on-hook and off-hook and noise pulses from the standard POTS telephones, and electrical systems such as heating and air conditioning systems, etc.
It is therefore important for a MAC to be informed of the conditions existing on a network at any time, and this is especially true in home network architectures. The status information is normally stored by the network controller in an external memory. In addition to the status information, the external memory also stores frame data and control information. The external memory, along with the PC board traces and connections, as well as parts of the logic within the network controller, comprise a memory subsystem. Failures in the memory subsystem may result from electrical or mechanical failure of any of the elements of the system and/or errors in the design of the PC board such as excessive loading or trace length.
In many networking and other products, an embedded memory built-in self test (MBIST) circuit is used to test the internal static random access memory (SRAM) at speed. Normally, this MBIST is a relatively simple circuit to read or write one memory location at each access. In more recent networking products, external SRAM has been more frequently employed in order to store the enormous amount of data required in networking applications. The external memories (SRAM) include different types of SRAM, including pipeline burst SRAM (or PB SRAM), No Bus Latency SRAM (or NoBL SRAM) and Zero Byte Turnaround SRAM (or ZBT SRAM).
For improved performance the above types of external memories allow bursting capability such that every external memory access may initiate multiple (e.g. four) memory locations consecutively. However, using a conventional MBIST that performs single write and single read accesses to test a burst type external memory does not fully test the external memory, since it fails to test the burst operations of the external memory.
There is a need for a method and arrangement for performing a built-in self test of both internal and external memory of a network interface controller, that adequately tests the capabilities of both types of memories.
This and other needs are met by embodiments of the present invention which provide a method of testing a memory arrangement of a network interface controller comprising the steps of determining whether the memory arrangement includes an external memory and an internal memory in relation to the network interface controller, and conducting a memory built-in self test (MBIST). When the memory arrangement includes both an external memory and an internal memory, the MBIST is conducted by performing back-to-back burst writing and reading operations on the external memory, and single accesses of external memory, followed by performing single accesses of memory locations of the internal memory. When the memory arrangement includes only an internal memory, the MBIST is conducted by performing single accesses of memory locations of the internal memory.
By performing back-to-back burst writing and reading operations, and single accesses of the external memory in the MBIST, adequate testing of the capabilities of the external memory is achieved. The test thus accounts for the burst capability of external memories used in network applications. In certain embodiments of the invention, the additional testing capability for external memories is added to a MBIST already used for testing internal memories with single accesses. This requires less hardware and does not add cost to a chip, such as a network interface controller.
The earlier stated needs are also met by another embodiment of the present invention which provides a network interface controller arrangement comprising a network interface controller having an internal memory, an external memory interface configured to couple an external memory to the network interface controller, and a memory built-in self test (MBIST) controller coupled to the internal memory and the external memory interface. The MBIST controller is configured to detect the presence of an external memory coupled to the external memory interface, and to conduct a MBIST on a detected external memory through the external memory interface and on the internal memory. The MBIST comprises back-to-back burst write and read operations on a detected external memory and single accesses of memory locations of the internal memory.
The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.